Design Through Verilog Hdl - by T R Padmanabhan & B Bala Tripura Sundari Hardcover

Book Synopsis

A comprehensive resource on Verilog HDL for beginners and experts

Large and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. Design Through Verilog HDL affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool.

Describing a design using Verilog is only half the story: writing test-benches, testing a design for all its desired functions, and how identifying and removing the faults remain significant challenges. Design Through Verilog HDL addresses each of these issues concisely and effectively. The authors discuss constructs through illustrative examples that are tested with popular simulation packages, ensuring the subject matter remains practically relevant.

Other important topics covered include:

• Primitives
• Gate and Net delays
• Buffers
• CMOS switches
• State machine design

Further, the authors focus on illuminating the differences between gate level, data flow, and behavioral styles of Verilog, a critical distinction for designers. The book's final chapters deal with advanced topics such as timescales, parameters and related constructs, queues, and switch level design.

Each chapter concludes with exercises that both ensure readers have mastered the present material and stimulate readers to explore avenues of their own choosing. Written and assembled in a paced, logical manner, Design Through Verilog HDL provides professionals, graduate students, and advanced undergraduates with a one-of-a-kind resource.

From the Back Cover

A comprehensive resource on Verilog HDL for beginners and experts

Large and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. Design Through Verilog HDL affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool.

Describing a design using Verilog is only half the story: writing test-benches, testing a design for all its desired functions, and how identifying and removing the faults remain significant challenges. Design Through Verilog HDL addresses each of these issues concisely and effectively. The authors discuss constructs through illustrative examples that are tested with popular simulation packages, ensuring the subject matter remains practically relevant. Other important topics covered include:

• Primitives
• Gate and Net delays
• Buffers
• CMOS switches
• State machine design

Further, the authors focus on illuminating the differences between gate level, data flow, and behavioral styles of Verilog, a critical distinction for designers. The book's final chapters deal with advanced topics such as timescales, parameters and related constructs, queues, and switch level design.

Each chapter concludes with exercises that both ensure readers have mastered the present material and stimulate readers to explore avenues of their own choosing. Written and assembled in a paced, logical manner, Design Through Verilog HDL provides professionals, graduate students, and advanced undergraduates with a one-of-a-kind resource.

Review Quotes

"...this book is surely welcome...due to its simple but efficient structure, the book can be used both in academia and in industry." (IEEE Circuits & Devices, July/August 2006)

"...ideally suited for teaching digital hardware design techniques using a low-level programming language...highly recommended..." (Choice, Vol. 41, No. 8, April 2004)

"...enables readers to master Verilog as an HDL for design...engages the readers at every stage through the variety and number of examples." (IEEE Solid-State Circuits Society Newsletter, January 2004)

About the Author

T. R. PADMANABHAN, PhD, is Dean-Engineering, Amrita Institute of Technology, Amrita Vishwa Vidyapeetham, (Amrita University), Ettimadai (PO), Coimbatore, India. He is a Senior Member of IEEE as well as a Fellow of both India's IE and IETE.

B. BALA TRIPURA SUNDARI is a Senior Lecturer in the ECE Department of the Amrita Institute of Technology. She is a senior faculty member in the microelectronics center at the institute. She is a member of India's IETE and ISTE.